FUJITSU CM71-00329-7E - Manual (Page 78)

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CHAPTER2 Dependence Functions
2.2.1.2 DRAM Refresh Control
This section explains DRAM refresh setup.
■ DRAM Refresh Control
The operating frequency of some DSU chips is automatically divided at a break (in emulation mode).
When this happens, the register (RFCR) must be reset if the built-in DRAM refresh function is used on the
user target.
The RFCR register values for On Execution (in user mode) and On Break (in emulation mode) can be set
by [RFCR] tab in debug environment setting dialog. When the mode is switched, the values set here are
used to set to the RFCR register.
Note:
When using chips with an operating frequency that is not divided automatically at a break (in
emulation mode), or when the built-in DRAM refresh function at the user target is not in use, this
function causes a slowdown in debugger operation due to writing to the RFCR register.