Monitoring line state—change detection, Deciding the width of data to acquire, Table 2-4. port and timing controller combinations – National Instruments 653X User Manual

Page 44: Monitoring line state—change detection -26, Deciding the width of data to acquire -26

Advertising
background image

Chapter 2

Using Your 653X

653X User Manual

2-26

ni.com

Note

If you are performing a finite pattern output operation, you can call the DIO Wait VI

instead of the DIO Write VI after the DIO Start VI. For more information about these VIs,
see the LabVIEW Help.

By default, for output buffered transfers the 6534 device will preload the on
board memory with data before starting the output operation. This is done
to eliminate or reduce the impact of the PCI bus bandwidth limitations and
increase the overall transfer rate. The preloading process will cause a small
delay between the start command in software and the actual start of data
transfer. If this is a concern, you may disable the preloading by calling the
following function/VI before the software start command:

NI-DAQ C interface—In the

Set_DAQ_Device_Info

function,

set the ND_FIFO_TRANSFER_COUNT to ND_NONE.

LabVIEW—In the DIO Parameter VI, set the Scarabs Preload Enable
attribute to OFF.

Monitoring Line State—Change Detection

You can configure your 653X device to acquire data whenever the state of
one or more data lines change. Once the 653X device detects a change in
one of the selected lines, it will capture data within 50–150 ns and outputs
a pulse on the REQ pin. This mode increases CPU and bus efficiency
because you can monitor activity on input lines without continuously
polling or transferring unnecessary data during periods of inactivity.

Tip

The 653X device used alone will detect if a change occurred, but if used in

conjunction with a 660X device (via a RTSI line), the relative time between changes can be
acquired by the 660X device.

Deciding the Width of Data to Acquire

You can choose between a width of eight, 16, or 32 bits. Use the following
table to find the valid combinations of ports and timing controllers you can
use based on the width of data you want to acquire.

Table 2-4. Port and Timing Controller Combinations

Transfer

Width

Possible Port

Combinations

Timing Controllers

That Can Be Used

8 bits

Port 0 (DIOA<0..7>)

Group 1

Port 2 (DIOC<0..7>)

Group 2

Advertising