Pxi express peripheral slots, System timing slot – National Instruments PXI Express NI PXIe-1065 User Manual
Page 15
Chapter 1
Getting Started
1-8
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PXI Express Peripheral Slots
There are three PXI Express peripheral slots: slots 8–10. Slot 8 is directly
connected to the system slot with a x4 PCI Express link. Slots 9 and 10 are
connected to the system slot through a PCI Express switch. PXI Express
peripheral slots can accept the following modules:
•
A PXI Express Peripheral with x4 or x1 PCI Express link to the system
slot or through a switch to the system slot.
•
A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
System Timing Slot
The System Timing Slot is slot 14. The system timing slot will accept the
following peripheral modules:
•
A PXI Express System Timing Module with x4 or x1 PCI Express link
to the system slot through a PCIe switch.
•
A PXI Express Peripheral with x4 or x1 PCI Express link to the system
slot through a PCIe switch.
•
A CompactPCI Express Type-2 Peripheral with x4 or x1 PCI Express
link to the system slot through a PCIe switch.
The system timing slot has 3 dedicated differential pairs (PXIe_DSTAR)
connected from the TP1 and TP2 connectors to the XP3 connector for each
PXI Express peripheral or hybrid peripheral slot, as well as routed back to
the XP3 connector of the system timing slot as shown in Figure 1-3. The
PXIe_DSTAR pairs can be used for high-speed triggering, synchronization
and clocking. Refer to the PXI Express Specification for details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 1-3 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module may source a 10MHz clock to which the backplane will
phase-lock. Refer to the
section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the
section of this
chapter for details.