Texas Instruments TMS320TCI6486 - Manual (Page 21)

MTCLK
MTXD[7−0]
MTXEN
MCOL
MCRS
MRCLK
MRXD[7−0]
MRXDV
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core Transformer
2.5 MHz,
25 MHz,
or 125 MHz
RJ−45
EMAC
MDIO
GMTCLK
www.ti.com EMAC Functional Architecture
Table 8. EMAC and MDIO Signals for RMII Interface (continued)
Signal Name I/O Description
RMRXER I Receive error (RMRXER). The receive error signal is asserted for one or more reference clock
periods to indicate that an error was detected in the received frame. This is meaningful only during
data reception when RMCRSDV is active. It is driven synchronously to the RMII reference clock.
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the
system. It is used to synchronize MDIO data access operations done on the MDIO pin. The
frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of
the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address,
register address, and data bit cycles. The MDIO pin acts as an output for everything except the data
bit cycles, when the pin acts as an input for read operations.
The 50-MHz reference clock (RMREFCLK) for the RMII gasket is sourced externally through a zero-delay
clock buffer. If multiple RMII PHY ports are used, all device RMII reference clocks must come from same
zero-delay clock buffer.
On the TCI6486/C6472 device, RMII pins are multiplexed with other non-RGMII pins. When using the
RMII0 port on EMAC0, there are no restrictions on the available EMAC1 Ethernet interfaces (RMII1,
S3MII1, and RGMII1 are useable). When using the RMII1 port on EMAC1, the EMAC0 Ethernet interfaces
not available due to pin multiplexing are GMII0/MII0. The RMII0, S3MII0, and RGMII0 ports are available
on EMAC0 Ethernet interfaces when using the RMII1 port on EMAC1.
If the device is interfaced to an Ethernet switch through the RMII interface, all device RMII reference
clocks should be externally sourced from the same zero-delay clock buffer.
2.3.3 Gigabit Media Independent Interface (GMII) Connections
Figure 4 shows a device with integrated EMAC and MDIO interfaced to the PHY via a GMII connection.
This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.
Figure 4. Ethernet Configuration with GMII Interface
The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps
mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface, and only the lower 4 bits of
data are transferred for each of the data buses.
Table 9 summarizes the individual EMAC and MDIO signals for the GMII interface.
21 SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO
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