Texas Instruments TMS320TCI6486 - Manual (Page 48)

EMIC
module
Control
registers
and logic
PHY
monitoring
Peripheral
clock
MDIO
clock
generator
USERINT
MDIO
interface
PHY
polling
MDCLK
MDIO
LINKINT
Configuration bus
EMAC Functional Architecture www.ti.com
Figure 21. MDIO Module Block Diagram
2.8.1.1 MDIO Clock Generator
The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock
(CPUCLK/6). The MDIO clock is specified to run up to 2.5 MHz, although typical operation would be 1.0
MHz. As the peripheral clock frequency is variable (CPUclk/6), the application software or driver controls
the divide-down amount.
2.8.1.2 Global PHY Detection and Link State Monitoring
The MDIO module enumerates all PHY devices in the system by continuously polling all 32 MDIO
addresses. The module tracks whether a PHY on a particular address has responded, and whether the
PHY currently has a link. This information allows the software application to quickly determine which
MDIO address the PHY is using, and if the system is using more than one PHY. The software application
can then quickly switch between PHYs based on their current link status.
2.8.1.3 Active PHY Monitoring
Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link state
by reading the PHY status register. The MDIO device stores link change events that may optionally
interrupt the CPU. Thus, the system can poll the link status of the PHY device without continuously
performing MDIO accesses. Up to two PHY devices can be actively monitored at any given time.
2.8.1.4 PHY Register User Access
When the DSP must access the MDIO for configuration and negotiation, the PHY access module performs
the actual MDIO read or write operation independent of the CPU. Thus, the CPU can poll for completion
or receive an interrupt when the read or write operation has been performed. There are two user access
registers (USERACCESS0 and USERACCESS1), allowing the software to submit up to two access
requests simultaneously. The requests are processed sequentially.
48 C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010
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