Texas Instruments TMS320TCI6486 - Manual (Page 62)

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Table 14. Receive Frame Treatment Summary (continued)
Address RXMBPENABLE Bits
Match
RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame Treatment
1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames
transferred to address match channel. No undersized/fragment
frames are transferred.
1 X 1 1 1 All address matching frames with and without errors transferred
to the address match channel.
2.11.9 Receive Overrun
The types of receive overruns are:
• FIFO start-of-frame overrun (FIFO_SOF)
• FIFO middle-of-frame overrun (FIFO_MOF)
• DMA start-of-frame overrun (DMA_SOF)
• DMA middle-of-frame overrun (DMA_MOF)
The statistics counters used to track these types of receive overruns are:
• Receive Start-of-Frame Overruns Register (RXSOFOVERRUNS)
• Receive Middle-of-Frame Overruns Register (RXMOFOVERRUNS)
• Receive DMA Overruns Register (RXDMAOVERRUNS)
Start-of-frame overruns happen when there are no resources available when frame reception begins.
Start-of-frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.
Middle-of-frame overruns happen when there are some resources to start the frame reception, but the
resources run out during frame reception. In normal operation, a frame that overruns after starting the
frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in
the RXMBPENABLE register affects overrun frame treatment.
Table 15 shows how the overrun condition
is handled for the middle-of-frame overrun.
Table 15. Middle-of-Frame Overrun Treatment
Address Match RXCAFEN RXCEFEN Middle-of-Frame Overrun Treatment
0 0 X Overrun frame filtered.
0 1 0 Overrun frame filtered.
0 1 1 As much frame data as possible is transferred to the promiscuous channel
until overrun. The appropriate overrun statistic(s) is incremented and the
OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note
that the RXMAXLEN number of bytes cannot be reached for an overrun to
occur (it would be truncated and be a jabber or oversize).
1 X 0 Overrun frame filtered with the appropriate overrun statistic(s) incremented.
1 X 1 As much frame data as possible is transferred to the address match
channel until overrun. The appropriate overrun statistic(s) is incremented
and the OVERRUN flag is set in the SOP buffer descriptor. Note that the
RXMAXLEN number of bytes cannot be reached for an overrun to occur (it
would be truncated).
2.12 Packet Transmit Operation
The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or
round robin as selected by the TXPTYPE bit in the MACCONTROL register. If the priority type is fixed,
then channel 7 has the highest priority and channel 0 has the lowest priority. Round robin priority
proceeds from channel 0 to channel 7.
2.12.1 Transmit DMA Host Configuration
To configure the transmit DMA for operation, the host must perform the following:
• Write the MACSRCADDRLO and MACSRCADDRHI registers (used for pause frames on transmit).
62 C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010
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