Texas Instruments TMS320TCI6486 - Manual (Page 86)

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4.11 MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR)
The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
Figure 38 and described in Table 31 .
Figure 38. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
31 16
Reserved
R-0
15 2 1 0
USERINT
Reserved
MASKCLEAR
R-0 R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 31. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 USERINTMASKCLEAR MDIO user command complete interrupt mask clear for USERINTMASKED[1:0]
respectively. Setting a bit to 1 will disable further user command complete interrupts for
that particular USERACCESS register. Writing a 0 to this register has no effect.
86 C6472/TCI6486 EMAC/MDIO SPRUEF8F – March 2006 – Revised November 2010
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