Texas Instruments TMS320TCI6486 - Manual (Page 55)

www.ti.com EMAC Functional Architecture
Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel
(RXnFREEBUFFER) is less than or equal to the channel flow control threshold register
(RXnFLOWTHRESH) value. Receive flow control is independent of receive QOS, except that both use the
free buffer values.
When enabled and triggered, receive FIFO flow control prevents further frame reception based on the
number of cells currently in the receive FIFO. Receive FIFO flow control may be enabled only in
full-duplex mode (FULLDUPLEX bit is set in the MACCONTROL register). Receive flow control prevents
reception of frames on the port until all of the triggering conditions clear, at which time frames may again
be received by the port.
Receive FIFO flow control is triggered when the occupancy of the FIFO is greater than or equal to the
RXFIFOFLOWTHRESH value in the FIFOCONTROL register. The RXFIFOFLOWTHRESH value must be
greater than or equal to 1h and less than or equal to 42h (decimal 66). The RXFIFOFLOWTHRESH reset
value is 2h.
Receive flow control is enabled by the RXBUFFERFLOWEN bit and the RXFIFOFLOWEN bit in the
MACCONTROL register. The FULLDUPLEX bit in the MACCONTROL register configures the EMAC for
collision or IEEE 802.3X flow control.
2.10.1.4 Collision-Based Receive Buffer Flow Control
Collision-based receive buffer flow control provides a means of preventing frame reception when the
EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam
sequence transmitted is the 12-byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3 in hexadecimal.
The jam sequence begins approximately when the source address starts to be received. These forced
collisions are not limited to a maximum of 16 consecutive collisions and are independent of the normal
back-off algorithm.
Receive flow control does not depend on the value of the incoming frame destination address. A collision
is generated for any incoming packet, regardless of the destination address, if any EMAC enabled
channel's free buffer register value is less than or equal to the channel's flow threshold value.
2.10.1.5 IEEE 802.3X Based Receive Buffer Flow Control
IEEE 802.3x based receive buffer flow control provides a means of preventing frame reception when the
EMAC is operating in full-duplex mode (the FULLDUPLEX bit is set in the MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC transmits a pause frame to request that the
sending station stop transmitting for the period indicated within the transmitted pause frame.
The EMAC transmits a pause frame to the reserved multicast address at the first available opportunity
(immediately if currently idle, or following the completion of the frame currently being transmitted). The
pause frame contains the maximum possible value for the pause time (FFFFh). The EMAC counts the
receive pause frame time (decrements FF00h to 0) and retransmits an outgoing pause frame, if the count
reaches zero. When the flow control request is removed, the EMAC transmits a pause frame with a zero
pause time to cancel the pause request.
Note that transmitted pause frames are only a request to the other end station to stop transmitting.
Frames that are received during the pause interval are received normally (provided the receive FIFO is not
full).
Pause frames are transmitted if enabled and triggered, regardless of whether or not the EMAC is
observing the pause time period from an incoming pause frame.
The EMAC transmits pause frames as described below:
• The 48-bit reserved multicast destination address 01.80.C2.00.00.01h.
• The 48-bit source address (set via the MACSRCADDRLO and MACSRCADDRHI registers).
• The 16-bit length/type field containing the value 88.08h.
• The 16-bit pause opcode equal to 00.01h.
• The 16-bit pause time value of FF.FFh. A pause-quantum is 512 bit-times. Pause frames sent to
cancel a pause request have a pause time value of 00.00h.
55 SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO
Submit Documentation Feedback
Copyright © 2006–2010, Texas Instruments Incorporated