Cirrus Logic CS1631 - Manual (Page 14)

CS1630/31
14 DS954F3
The reference currents are the required values at ambient
temperature T
A
= 25ºC and dim = 100%. They are multiplied
by the appropriate gains, and these values are passed to the
final power stage. The CS1630/31 uses polynomial
approximations in one and two dimensions to generate the
color gains. These polynomials can be up to third-order.
GAIN
DTR
approximations create a custom temperature
compensation profile and dimming profile of the temperature-
sensitive LEDs (see Equation 1). Profiles are programmed
through the Color Polynomial Coefficient registers (see "Color
Polynomial Coefficient (P30, P20, P10, P03, P02, P01, P21,
P12, P11, P00) – Address 5 - 24" on page 29).
GAIN
DR
approximation allows custom dimming profile of the
white LEDs (see Equation 2). The profile is programmed
through the Color Polynomial Coefficient registers (see "Color
Polynomial Coefficient (Q3, Q2, Q1, Q0) – Address 25 - 32" on
page 30).
Cirrus Logic, Inc. and its affiliates and subsidiaries generally
make no representations or warranties that the combination of
Cirrus Logic’s products with light-emitting diodes (“LEDs”),
converter materials, and/or other components will not infringe
any third-party patents, including any patents related to color
mixing in LED lighting applications, such as, for example, U.S.
Patent No. 7,213,940 and related patents of Cree, Inc. For
more information, please see Cirrus Logic’s Terms and
Conditions of Sale, or contact a Cirrus Logic sales
representative.
5.5 Dimming Signal Extraction and the
Dim Mapping Algorithm
When operating with a dimmer, the dimming signal is
extracted in the time domain and is proportional to the
conduction angle of the dimmer. A control variable is passed
to the quasi-resonant second stage to achieve output currents
from 0% to 100%.
5.6 Boost Stage
The high-voltage FET in the source-follower startup circuit is
source-switched by a variable current source on the SOURCE
pin to operate a boost circuit. Peak FET switching current is
set by the PEAK_CUR register (see "Peak Current
(PEAK_CUR) – Address 51" on page 39).
In No-dimmer Mode, the boost stage begins operating when
the start threshold is reached during each rectified half line-cy-
cle and is disabled at the nominal boost output voltage. The
peak FET switching current determines the percentage of the
rectified input voltage conduction angle over which the boost
stage will operate. The control algorithm adjusts the peak FET
switching current to maximize the operating time of the boost
stage, thus improving the input power factor.
When operating in Leading-edge Mode, the boost stage
ensures the hold current requirement of the dimmer is met
from the initiation of each half-line dimmer conduction cycle
until the peak of the rectified input voltage. Trailing-edge Mode
boost stage ensures that the trailing-edge is exposed at the
correct time with the correct current.
5.6.1 Maximum Peak Current
The maximum boost inductor peak current is configured by
adjusting the peak switching current with peak current
code I
PK(code)
. The PEAK_CUR register (see "Peak Current
(PEAK_CUR) – Address 51" on page 39) is used to store peak
current code I
PK(code)
. Maximum power output is proportional
to peak current code I
PK(code)
, as shown in Equation 3:
where,

= the correction term at 0.55
V
RMS(typ)
= nominal operating input RMS voltage
I
PK
= peak current code I
PK(code)

4.1mA
where,
T = the measured normalized temperature and is 0

T

1.0
D = the normalized dim value and is 0

D

1.0
GAIN
DTR
= gain of the channel based on the temperature measurement and the dim value:
where,
D = the normalized dim value and is 0

D

1.0
GAIN
DR
= gain of the channel based on the dim value
GAINDTR P30 T
3
 P20 T
2
 P10 + + T  P03 D
3
 P02 + + D
2
 P01 D  P21 T
2
D   + + = P12 T D
2
  P11 T D   P00 + + + [Eq.1]
GAIN
DR
Q3 = D
3
 Q2 D
2
 Q1 D  Q0 + + +
[Eq.2]
P
IN max  

I
PK
V
RMS typ  
  
2
------------------------------------------------ = [Eq.3]