Cirrus Logic CS1631 - Manual (Page 25)

CS1630/31
DS954F3 25
5.11.4 Write Operation
To perform a write operation, the master must write the 7-bit
device address, the R/W bit, the BLK/SGL bit, and the 7-bit
shadow register address. The master can then write the
required bytes to the shadow registers. Figure 29 illustrates
protocol for a single and block write operation.
To perform a single shadow register write, a write to the
Control Port must be used to set up the shadow register
address and the BLK/SGL configuration bit (indicating a single
write operation). To initiate a single write operation, a Start
condition followed by a slave address of 0x20 (7 MSB device
address = ‘0010000’ and the LSB R/W = ‘0’ for a write
operation) is sent at the start of the message. The most
significant bit of the second byte is cleared to ‘0’ to indicate a
single byte write. The remaining 7 bits of the second byte
represent the shadow register address of the write operation.
After receiving the Acknowledge from the Control Port, the
master should terminate the message by sending a Stop
condition. The protocol for a single write operation is shown as
the top frame in Figure 29.
To initiate a block write operation, a Start condition followed by
a slave address of 0x20 (7 MSB device address =
‘0010000’and the LSB R/W = ‘0’ for a write operation) is sent
at the start of the message. The MSB of the second byte is set
to ‘1’ to indicate a block write. The remaining 7 bits of the
second byte represent the starting shadow register address of
the write operation. The slave continues to send data bytes
until the master sends a Stop condition after receiving the
Acknowledge, signifying the end of the block write message.
The protocol for a block write operation is illustrated by the
bottom frame in Figure 29. Block writes will wrap around from
shadow register address 127 to 0 if a Stop condition is not
received.
5.11.5 Customer I 2 C Lockout
The CS1630/31 provides a mechanism that locks or disables
the I
2 C control port. This feature provides security against
potential access to proprietary register settings and OTP
memory (color compensation) through the I
2
C control port. To
enable the lockout feature, the LOCKOUT bit is set to ‘1’ in the
Config0 register (see "Configuration 0 (Config0) – Address 0"
on page 29) and setting a 32-bit Lockout Key in registers
LOCK3, LOCK2, LOCK1, and LOCK0 (at register address
0x01 to 0x04). The value of the Lockout Key is user
programmable and stored in OTP memory (see "Lockout Key
(LOCK0, LOCK1, LOCK2, LOCK3) – Address 1 - 4" on
page 29).
To unlock the Control Port, the proper programmed Lockout
Key is written to the 32-bit Lockout Key shadow registers
LOCK3, LOCK2, LOCK1, and LOCK0. The Lockout Key must
be written in ascending address order for the lockout to be
disabled. The MODE bit in register Config0 is set to ‘1’, the
Color Polynomial Coefficient registers P10_MSB, P10_LSB,
P01_MSB, and P01_LSB (at register address 0x09, 0x0A,
0x0F, and 0x10) are appended to the Lockout Key to increase
security. If the wrong Lockout Key is written to the shadow
resisters when attempting to disable the lockout feature, the
part cannot be unlocked until a reset cycle occurs.
In lockout mode, the Control Port disables the following
operations through the I
2 C communication port:
• I 2 C read operations from OTP shadow registers (value
of 0x0 will be read through control port)
• I 2 C write operations to lockout enabled or key shadow
registers (including read operations through PLC)
• Direct OTP memory read or write (including reads/writes
through PLC)
Write operations to either OTP or test space (except OTP
Lockout Key) are allowed in lockout mode.
Figure 29. Frame Formats for Write Operation
0 A 0 S A
Device Address
(7-bit)
Register Address
(7-bit)
‘0’ = Single ‘0’ = Write Start
Condition
Stop
Condition
Data Transferred
(1 Byte and Acknowledge)
Slave Address
(1 Byte and Acknowledge)
P A Data
‘A’ = Acknowledge
(SDA Low)
‘1’ = Block
S A
Device Address
(7-Bit)
Register Address
(7-Bit)
Data
… ...
From Slave to Master
From Master to Slave
‘0’ = Write Start
Condition
Stop
Condition
‘A’ = Acknowledge (SDA Low)
Data Transferred
(n Bytes and Acknowledge)
0 A 1 A
Slave Address
(1 Byte and Acknowledge)
P A Data