Cirrus Logic CS1631 - Manual (Page 24)

CS1630/31
24 DS954F3
whether data transfer is a read or write operation. This bit
should be set to '0' to perform a write operation and '1' to
perform a read operation. The 7-bit device address is the 7
most significant bit of the slave address. For data transfers,
the CS1630/31 acknowledges a binary device address of
‘0010000’, which is reserved for accessing OTP shadow
registers (see "One-Time Programmable (OTP) Registers" on
page 27).
After the 7-bit device address is received, the Control Port
performs a compare to determine if it matches the CS1630/31
device address. If the compare is true, the Control Port will
respond with an Acknowledge (bit A) and prepares the device
for a read or write operation. The final bit is the Stop condition
(bit P), which is sent by the master to finish a data transfer.
The communication port supports single and block data
transfers. The block read or write capability is available by
setting the MSB of the register address to ‘1’. Device address
0x10 provides access to the OTP shadow registers in the
address range of 0x00 to 0x7F.
5.11.2 Control Port Enable
Control Port mode is enabled and initiated by transmitting a
two-byte hardware pass code using an I
2 C block write.
To enable the control port, the master needs to write a Start
condition followed by a slave address of 0x22 (7 MSB device
address = ‘0010001’ and the LSB R/W = ‘0’ for a write
operation). Then a 0x81 (MSB BLK/SGL = ‘1’ and 7 LSB
register address = ‘0000001’) followed by two bytes of data
0xF4 and 0x4F, ending the transmission with a Stop condition.
Once in Control Port mode, the CS1630/31 can be configured
to perform color calibration functions and program the OTP
memory. Several other system configuration tasks can be
performed by writing and reading the shadow registers using
the I
2 C port.
5.11.3 Read Operation
To enter a read operation, the master must set up the Control
Port by writing a Start condition, the 7-bit device address, the
R/W bit, the Block/Single (BLK/SGL) bit, and the 7-bit shadow
register address. The master can then perform a read
operation to retrieve the required bytes from the shadow
registers. Figure 28 illustrates the protocol for a single and
block read operation.
To perform a single shadow register read, a write to the
Control Port must be used to set up the shadow register
address and the BLK/SGL configuration bit (indicating a single
read operation). To enter a single read operation, a Start
condition followed by a slave address of 0x20 (7 MSB device
address = ‘0010000’ and the LSB R/W = ‘0’ for a write
operation) is sent at the start of the message. The MSB of the
second byte is cleared to ‘0’ to indicate a single byte read. The
remaining 7 bits of the second byte represent the shadow
register address of the read operation. To perform the single
read operation, a Start condition followed by a slave address
of 0x21 (7 MSB device address = ‘0010000’ and the LSB
R/W = ‘1’ for a read operation) is sent at the start of the
operation. After receiving the byte of data, the master should
terminate the message by sending a Not Acknowledge
followed by a Stop condition. The protocol for a single read
operation is illustrated by the top frame in Figure 28.
To enter a block read operation, the master must set up the
Control Port by writing a Start condition followed by a slave
address of 0x20 (7 MSB device address = ‘0010000’ and the
LSB R/W = ‘0’ for a write operation) at the start of the
message. The MSB of the second byte is set to ‘1’ to indicate
a block read. The remaining 7 bits of the second byte
represent the starting shadow register address of the read
operation. To perform the block read operation, a Start
condition followed by a slave address of 0x21 (7 MSB device
address = ‘0010000’ and the LSB R/W = ‘1’ for a read
operation) is sent at the start of the operation. The slave
continues to send data bytes until the master sends a Not
Acknowledge followed by a Stop condition, signifying the end
of the block read operation. The protocol for a block read
operation is illustrated by the bottom frame in Figure 28.
Figure 28. Frame Formats for Read Operation
0 A 0 S A
Device Address
(7-bit)
Register Address
(7-bit)
‘0’ = Single ‘0’ = Write Start
Condition
Stop
Condition
Data Transferred
(1 Byte and Acknowledge)
Slave Address
(1 Byte and Acknowledge)
P A Data
‘A’ = Acknowledge
(SDA Low)
‘1’ = Block
S A
Device Address
(7-Bit)
Register Address
(7-Bit)
Data
… ...
From Slave to Master
From Master to Slave
‘0’ = Write Start
Condition
Stop
Condition
Data Transferred
(n Bytes and Acknowledge)
0 A 1 A
Slave Address
(1 Byte and Acknowledge)
P A Data Data Data
A 1 S
Device Address
(7-bit)
‘1’ = Read
Slave Address
(1 Byte and Acknowledge)
S
Device Address
(7-Bit)
‘1’ = Read
1 A
Slave Address
(1 Byte and Acknowledge)
‘A’ = Acknowledge
(SDA Low)