Cirrus Logic CS5373A - Manual (Page 16)

CS5373A
16 DS703F2
DIGITAL CHARACTERISTICS (CONT.)
Notes: 32. MCLK is generated by the CS5378 digital filter. If MCLK is disabled, the device automatically enters a
power-down state.
33. MSYNC is generated by the CS5378 digital filter and is latched on MCLK rising edge, synchronization
instant (t
0
) on next MCLK rising edge.
34. TDATA can be delayed from 0 to 63 full bit periods by the test bit stream generator in the CS5378 digital
filter. The timing diagrams show no TBSDATA delay.
35. Decimated, filtered, and offset corrected 24-bit output word from the CS5378 digital filter.
36. TDATA is generated by the test bit stream generator in the CS5378 digital filter.
37. TBSGAIN register value in the CS5378 digital filter.
Parameter Symbol Min Typ Max Unit
Master Clock Input
MCLK Frequency ( Note 32 ) f
CLK
- 2.048 - MHz
MCLK Period ( Note 32 ) t
mclk
- 488 - ns
MCLK Duty Cycle ( Note 10 ) MCLK
DC
40 - 60 %
MCLK Rise Time ( Note 10 ) t
RISE
- - 50 ns
MCLK Fall Time ( Note 10 ) t
FALL
- - 50 ns
MCLK Jitter (In-band or aliased in-band) ( Note 10 ) MCLK
IBJ
- - 300 ps
MCLK Jitter (Out-of-band) ( Note 10 ) MCLK
OBJ
- - 1 ns
Master Sync Input
MSYNC Setup Time to MCLK Rising ( Note 10, 33 ) t
mss
20 122 - ns
MSYNC Period ( Note 10, 33 ) t
msync
40 976 - ns
MSYNC Hold Time after MCLK Falling ( Note 10, 33 ) t
msh
20 122 - ns
MSYNC Instant to TDATA Start ( Note 34 ) t
tdata
- 1220 - ns
MDATA Output
MDATA Output Bit Rate f
mdata
- 512 - kbits/s
MDATA Output One’s Density Range ( Note 10 ) MDAT
OD
14 - 86 %
Full-scale Output Code ( Note 35 ) MDAT
FS
0xA2EAAE - 0x5D1C41
TDATA Input
TDATA Input Bit Rate ( Note 36 ) f
tdata
- 256 - kbits/s
TDATA Input One’s Density Range ( Note 10 ) TBS
OD
25 - 75 %
TBSGAIN Full-scale Code ( Note 37 ) TBS
FS
- 0x04B8F2 -
TBSGAIN -20 dB Code ( Note 37 ) TBS
-20dB
- 0x0078E5 -