Cirrus Logic CS5373A - Manual (Page 27)

CS5373A
DS703F2 27
6.3 MDATA Connection
The CS5373A modulator outputs a
ΔΣ serial
bit stream to the MDATA pin, with a one’s den-
sity proportional to the differential amplitude of
the analog input signal. The output bit rate
from the MDATA output is a divide-by-four of
the input master clock, and so is nominally
512 kHz.
The MDATA output has a nominal 50% one’s
density for mid-scale input, approximately
86% one’s density for a positive full-scale in-
put, and approximately 14% one’s density for
a negative full-scale input. One’s density of the
MDATA output is defined as the ratio of ‘1’ bits
to total bits in the serial bit stream output, i.e.
an 86% one’s density has, on average, a ‘1’
value in 86 of every 100 output data bits.
6.4 MFLAG Connection
The CS5373A
ΔΣ modulator has a 4 th
order ar-
chitecture which is conditionally stable and
may go into an oscillatory condition if the ana-
log inputs are over-ranged more than 5% past
either positive or negative full-scale.
If an unstable condition is detected, the modu-
lator collapses to a 1
st
order system and tran-
sitions the MFLAG output low-to-high to signal
an error condition to the CS5378 digital filter.
The analog signal must be reduced to within
the full-scale input range for at least 32 MCLK
cycles for the modulator to recover from an os-
cillatory condition. If the analog input remains
over-ranged for an extended period, the mod-
ulator will cycle between 4
th
order and 1
st
or-
der operation and the MFLAG output will be
seen to pulse.
The MFLAG output connects to a dedicated in-
put on the CS5378 digital filter, causing an er-
ror flag to be set in the status portion of the
next conversion output data word.
6.5 TDATA Connection
The TDATA digital input to the test DAC ex-
pects encoded one-bit
ΔΣ data nominally at a
256 kHz rate. The one’s density input range is
approximately 25% minimum to 75% maxi-
mum, with differential mid-scale at 50% one’s
density.
The CS5378 digital filter test bit stream (TBS)
generator can encode two types of AC signals
as over-sampled, one-bit
ΔΣ data – a pure sine
wave for THD and CMRR testing or a trigger-
able impulse waveform for synchronization
testing and impulse response characteriza-
tion. In the AC test modes, the test DAC con-
verts the over-sampled test bit stream digital
data into precision differential or common
mode analog AC signals.
The CS5378 TBS sine mode encodes an ap-
proximately 5 V
pp
full-scale sine wave signal
with a digital filter TBSGAIN register setting of
0x04B8F2. Because TBS impulse mode en-
codes frequencies above 100 Hz, a maximum
0x0078E5 TBSGAIN impulse mode register
setting is specified to guarantee stability of the
DAC low-power
ΔΣ circuitry. Details on the set-
up and operation of the digital filter test bit-
stream (TBS) generator can be found in the
CS5378 data sheet.
6.6 GPIO Connections
The CS5378 controls 8 general-purpose input
output (GPIO) pins through the digital filter
GPCFG register. These GPIO pins are typical-
ly assigned to operate the CS5373A mode and
attenuator pins, along with the CS3301A/02A
amplifier input mux and gain pins. The gain
and attenuation settings of the CS3301A/02A
amplifiers and the CS5373A test DAC are
identically decoded to allow full-scale perfor-
mance testing at all system gain ranges with
shared GAIN and ATT control signals.
If precise timing control of operational modes
is required (for example, switching between
DC modes for pulse generation), an external
controller should directly toggle the MODE
pins of the CS5373A to avoid the delay asso-
ciated with writing to the CS5378 digital filter
GPCFG register.