Cirrus Logic CS5373A - Manual (Page 19)

CS5373A
DS703F2 19
2. GENERAL DESCRIPTION
The CS5373A is a high-performance, fourth-
order
ΔΣ modulator integrated with a digital-to-
analog converter (DAC). When combined with
a CS3301A/02A differential amplifier and the
CS5378 digital filter, a small low-power self-
testing high-accuracy single-channel mea-
surement system results.
2.1 Delta-Sigma Modulator
The CS5373A modulator has high dynamic
range and low total harmonic distortion with
very low power consumption, and is optimized
for extremely high-resolution measurement of
5 V
pp
or smaller differential signals. It converts
analog input signals between DC and 1720 Hz
to an oversampled serial bit stream at
512 kbits per second.
The CS5378 digital filter generates the clock
and synchronization inputs for the modulator
while receiving the modulator one-bit data and
over-range flag outputs. The digital filter then
decimates the modulator’s oversampled out-
put bit stream to a 24-bit output at the selected
output word rate.
2.2 Digital-to-Analog Converter
The CS5373A test DAC is driven by a digital
ΔΣ bit stream from the CS5378 digital filter’s
test bit stream (TBS) generator and operates
in either AC or DC test modes. AC test modes
(MODE 1, 2, 3, 6) are used to measure sys-
tem THD and CMRR performance. DC test
modes (MODE 4, 5) are for gain calibration
and pulse tests. The digital filter also provides
clock and syncronization signals as well as
GPIO control signals to set the operational
mode and analog output attenuation.
Two sets of differential analog outputs, OUT
and BUF, simplify system design as dedicated
outputs for testing the electronics channel and
for in-circuit sensor tests. Output attenuator
settings are binary weighted (1, 1/2, 1/4, 1/8,
1/16, 1/32, 1/64) and match the CS3301A/02A
amplifier input levels for full-scale testing at all
gain ranges.
For maximum performance, the precision out-
puts (OUT±) must drive only high-impedance
loads such as the CS3301A/02A amplifier in-
puts. The buffered outputs (BUF±) can drive
lower-impedance loads, down to 1 k
Ω, but with
reduced performance compared to the preci-
sion outputs.
The test DAC is optimized for low-power oper-
ation and has a restricted operational band-
width in the AC modes. For stable operation,
full-scale AC test signals must not contain fre-
quencies above 100 Hz. AC test signals above
100 Hz (TBS impulse mode, for example)
must have a -20 dB reduced amplitude to en-
sure stability of the low-power
ΔΣ architecture.
24-Bit
ΔΣ
Test DAC
Attenuator
1/1 to 1/64
Clock
Generator
VA+
MODE(0, 1, 2) ATT(0, 1, 2)
VD
VA-
VREF+ VREF-
GND
MCLK
MSYNC
24-Bit
ΔΣ
Modulator
OUT+
OUT-
BUF+
BUF-
TDATA
CAP+
CAP-
MDATA
MFLAG
INR+
INF+
INF-
INR-
Figure 6. CS5373A Block Diagram