Cirrus Logic CS5373A - Manual (Page 17)

CS5373A
DS703F2 17
DIGITAL CHARACTERISTICS (CONT.)
MCLK
MSYNC
t
MDATA
TDATA
0
(2.048 MHz)
(512 kHz)
(256 kHz)
SYNC
MFLAG
Figure 4. System Timing Diagram
MCLK
MSYNC t
TDATA
0
(2.048 MHz)
(256 kHz)
t
mss t
mclk
t
msync
t
msh
MDATA
(2.048 MHz)
MFLAG
t
tdata
Figure 5. MCLK / MSYNC Timing Detail