Cirrus Logic CS5373A - Manual (Page 31)

CS5373A
DS703F2 31
8. VOLTAGE REFERENCE
The CS5373A requires a 2.500 V precision
voltage reference to be supplied to the VREF
±
pins.
8.1 VREF Power Supply
To guarantee proper regulation headroom for
the voltage reference device, the voltage refer-
ence GND pin should be connected to VA- in-
stead of system ground, as shown in
Figure 16 . This connection results in a VREF-
voltage equal to VA- and a VREF+ voltage
very near ground [(VA-) + 2.500 VREF].
Power supply inputs to the voltage reference
device should be bypassed to system ground
with 0.1
μF capacitors placed as close as pos-
sible to the power and ground pins. In addition
to 0.1
μF local bypass capacitors, at least
100
μF of bulk capacitance to system ground
should be placed on each power supply near
the voltage regulator outputs. Bypass capaci-
tors should be X7R, C0G, tantalum, or other
high-quality dielectric type.
8.2 VREF RC Filter
A primary concern in selecting a precision volt-
age reference device is noise performance in
the measurement bandwidth. The
Linear
Technology LT1019AIS8-2.5 voltage refer-
ence yields acceptable noise levels if the out-
put is filtered with a low-pass RC filter.
A separate RC filter is required for each sys-
tem device connected to a given voltage refer-
ence. By sharing a common RC filter, signal-
dependent sampling of the voltage reference
by one system device could cause unwanted
tones to appear in the measurement band-
width of another system device via common
impedance coupling.
8.3 VREF PCB Routing
To minimize the possibility of outside noise
coupling into the CS5373A voltage reference
input, the VREF
± traces should be routed as a
differential pair from the large capacitor of the
voltage reference RC filter. Careful control of
the voltage reference source and return cur-
rents by routing VREF
± as a differential pair
will improve immunity from external noise.
To further improve noise rejection of the
VREF
± routing, include 0.1
μF bypass ca-
pacitors to system ground as close as possible
to the VREF+ and VREF- pins of the
CS5373A.
8.4 VREF Input Impedance
The switched-capacitor input architecture of
the VREF
± inputs results in an input imped-
ance that depends on the internal capacitor
size and the clock frequency. With a 15 pF in-
ternal capacitor and a 2.048 MHz MCLK the
VREF input impedance is approximately
[1 / [(2.048 MHz) * (15 pF)]] = 32 k
Ω. While
the size of the internal capacitor is fixed, the
voltage reference input impedance will vary
10
Ω
To VREF+
+
From VA+
Regulator
2.500 V
VREF
0.1 μF
To VREF-
0.1 μF 100 μF
0.1 μF
0.1 μF
0.1 μF
100 μF
100 μF
From VA-
Regulator
Route VREF ± as a differential pair
from the 100uF RC filter capacitor
Figure 16. Voltage Reference Circuit