Cirrus Logic CS5373A - Manual (Page 24)

CS5373A
24 DS703F2
Differential AC test signals out of the CS5373A
consist of two halves with equal but opposite
magnitude, varying about a common mode
voltage. A full-scale 5 V
PP
differential AC sig-
nal centered on a -0.15 V common mode volt-
age will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIG-
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIG-
So the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 V
pp
differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 V
pp
differ-
ential signal centered on a -0.15 V common
mode voltage never exceeds +1.1 V with re-
spect to ground and never drops below -1.4 V
with respect to ground on either half. By defini-
tion, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would correctly read 1.767 V
rms
, or 5 V
pp
.
5.2.2 AC Common Mode
The final AC test mode (MODE 6) enables the
modulator and AC test circuitry to create a
matched AC common mode analog signal for
CMRR testing of the measurement channel. In
mode 6, both sets of analog outputs (OUT and
BUF) are enabled. There is no AC common
mode output for an attenuator setting of 1/64.
Gross leakage in the sensor channel can be
detected by applying a full-scale AC common
mode signal. If there is a significant differential
mismatch in the channel due to sensor leak-
age, the AC common mode signal will be con-
verted to a measurable differential signal at
the fundamental frequency.
5.2.3 DAC Stability
For the CS5373A’s low-power
ΔΣ DAC archi-
tecture to remain stable, the TDATA input bit
stream should only encode 100 Hz or lower
bandwidth analog signals. For TDATA bit
stream frequencies above 100 Hz (for exam-
ple, TBS impulse mode), the encoded ampli-
tude must be reduced -20 dB below full scale
to guarantee stability.
If the CS5373A’s low-power
ΔΣ DAC architec-
ture becomes unstable, persistent elevated
noise will be present on the analog outputs
and AC linearity will be poor. To recover stabil-
ity, place the CS5373A into power down or
sleep mode and restart the CS5378 test bit
stream generator before placing the CS5373A
back into an AC test mode.
5.3 DC Test Modes
DC test modes enable the modulator and DC
test circuitry to create precision level-shifted
and buffered versions of the voltage reference
input as precision DC common mode and DC
differential analog outputs. The absolute accu-
racy of the DC test modes is highly dependent
on the absolute accuracy of the voltage refer-
ence input voltage.
5.3.1 DC Common Mode
The first DC test mode (MODE 4) enables the
modulator and DC test circuitry to create a
matched DC common mode analog output
voltage as a baseline measurement for gain
OUT+
OUT-
BUF+
BUF-
CS5373A
MODE 6
Maximum
2.5 Vpp
Common
Mode
Maximum
2.5 Vpp
Common
Mode
Figure 11. AC Common Mode