Cirrus Logic CS61880 - Manual (Page 25)

CS61880
DS450PP3 25
TNEG/UBS “High” for more than 16 TCLK cy-
cles. Transmit data is input to the part via the
TPOS/TDATA pin on the falling edge of TCLK.
When operating the part in hardware mode, the
CODEN pin is used to select between HDB3 or
AMI encoding. During host mode operation, the
line coding is selected via the
Line Length Chan-
nel ID Register (10h) (See Section 14.17 on
page 38).
NOTE: The encoders/decoders are selected for all
eight channels in both hardware and host
mode.
9.3 RZ Mode
In RZ mode, the internal pulse shape circuitry is
bypassed and RZ data driven into TPOS/TNEG is
transmitted on TTIP/TRING. In this mode, the
pulse width of the transmitter output is determined
by the width of the RZ signal input to TPOS/TNEG
pins. This mode is entered when MCLK is inactive
and TCLK is held “High” for at least 12
µ
s.
9.4 Transmitter Powerdown / High-Z
The transmitters can be forced into a high imped-
ance, low power state by holding TCLK of the ap-
propriate channel low for at least 12
µ
s or 140
MCLK cycles. In hardware and host mode, the
TXOE pin forces all eight transmitters into a high
impedance state within 1
µ
s.
In host mode, each transmitter is individually con-
trollable using the
Output Disable Register (12h)
(See Section 14.19 on page 38). The TXOE pin can
be used in host mode, but does not effect the con-
tents of the Output Enable Register. This feature is
useful in applications that require redundancy.
9.5 Transmit All Ones (TAOS)
When TAOS is activated, continuous ones are
transmitted on TTIP/TRING using MCLK as the
transmit timing reference. In this mode, the TPOS
and TNEG inputs are ignored.
In hardware mode, TAOS is activated by pulling
TCLK “High” for more than 16 MCLK cycles.
In host mode, TAOS is generated for a particular
channel by asserting the associated bit in the
TAOS
Enable Register (03h) (See Section 14.4 on
page 35).
Since MCLK is the reference clock, it should be of
adequate stability.
9.6 Automatic TAOS
While a given channel is in the LOS condition, if
the corresponding bit in the
Automatic TAOS
Register (0Eh) (See Section 14.15 on page 37) is
set, the device will drive that channel’s TTIP and
TRING with the all ones pattern. This function is
only available in host mode. Refer to
Loss-of-Sig-
nal (LOS) (See Section 10.5 on page 27).
9.7 Driver Failure Monitor
In host mode, the Driver Failure Monitor (DFM)
function monitors the output of each channel and
sets a bit in the
DFM Status Register (05h) (See
Section 14.6 on page 35) if a secondary short cir-
cuit is detected between TTIP and TRING. This
generates an interrupt if the respective bit in the
DFM Interrupt Enable Register (07h) (See Sec-
tion 14.8 on page 36) is also set. Any change in the
DFM Status Register (05h) (See Section 14.6 on
page 35) will result in the corresponding bit in the
DFM Interrupt Status Register (09h) (See Sec-
tion 14.10 on page 36) being set. The interrupt is
cleared by reading the
DFM Interrupt Status
Register (09h) (See Section 14.10 on page 36).
9.8 Driver Short Circuit Protection
The CS61880 provides driver short circuit protec-
tion when current on the secondary exceeds 50 mA
RMS.