Cirrus Logic CS61880 - Manual (Page 36)

CS61880
36 DS450PP3
14.7 LOS Interrupt Enable Register (06h)
14.8 DFM Interrupt Enable Register (07h)
14.9 LOS Interrupt Status Register (08h)
14.10 DFM Interrupt Status Register (09h)
14.11 Software Reset Register (0Ah)
14.12 Performance Monitor Register (0Bh)
14.13 Digital Loopback Reset Register (0Ch)
BIT NAME Description
[7:0] LOSE 7-0 Any change in a LOS Status Register will cause the INT pin to go low if corresponding bit in
this register is set to “1”. Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] DFME 7-0
Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit
will cause an interrupt if the corresponding bit is set to “1” in this register. Register bits
default to 00h after power-up or reset.
BIT NAME Description
[7:0] LOSI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the LOS Status Regis-
ter. The bits in this register indicate a change in status since the last cleared LOS interrupt.
Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] DFMI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the DFM Status Regis-
ter. The bits in this register indicate a change in status since the last cleared DFM interrupt.
Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to
00h after power-up or reset.
BIT NAME Description
[7:4] RSVD 7-4 RESERVED (These bits must be set to 0.)
[3:0] A[3:0] The G.772 Monitor is directed to a given channel based on the state of the four least signifi-
cant bits of this register. Register bits default to 00h after power-up or reset. The follow-
ing table shows the settings needed to select a specific channel’s receiver or transmitter to
perform G.772 monitoring. See
Table 6 on page 22 for G.772 Monitor Settings.
BIT NAME Description
[7:0] DLBK 7-0 Setting register bit n to “1” enables the digital loopback for channel n. Refer to Digital Loop-
back (See Section 12.3 on page 30) for a complete explanation. Register bits default to
00h after power-up or reset.