Cirrus Logic CS61880 - Manual (Page 65)

CS61880
DS450PP3 65
A[4:0]
D[7:0]
ALE
RDY
WR
(pulled high)
CS
HIGH-Z
1
7
10
HIGH-Z
11 12
2
5
3
4
6
ADDRESS
Write Data
Figure 29. Parallel Port Timing - Write; Intel Non-Multiplexed Address / Data Bus Mode
A[4:0]
D[7:0]
ALE
RDY
RD
(pulled high)
CS
HIGH-Z
1
9
10
HIGH-Z
11 12
2
5
3
4
8
ADDRESS
Read Data
Figure 30. Parallel Port Timing - Read; Intel Non-Multiplexed Address / Data Bus Mode