Pin out - 160-ball fbga package, Figure 2. cs61880 160-ball fbga package pin outs – Cirrus Logic CS61880 User Manual
Page 8
CS61880
8
DS450PP3
2. PIN OUT - 160-BALL FBGA PACKAGE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLKE
TDO
CBLSEL
REF
TPOS
5
RPOS
4
TPOS
4
RPOS
5
TPOS
2
RPOS
3
TPOS
3
RPOS
2
TTIP
5
TRING
4
TTIP
4
TRING
5
TTIP
2
TRING
3
TTIP
3
TRING
2
TGND
5
TGND
4
TGND
4
TGND
5
TGND
2
TGND
3
TGND
3
TGND
2
RRING
5
RTIP
4
RRING
4
RTIP
5
RRING
2
RTIP
3
RRING
3
RTIP
2
RRING
6
RTIP
7
RRING
7
RTIP
6
RRING
1
RTIP
0
RRING
0
RTIP
1
TGND
6
TGND
7
TGND
7
TGND
6
TGND
1
TGND
0
TGND
0
TGND
1
TTIP
6
TRING
7
TTIP
7
TRING
6
TTIP
1
TRING
0
TTIP
0
TRING
1
TVCC
6
TVCC
7
TVCC
7
TVCC
6
TVCC
1
TVCC
0
TVCC
0
TVCC
1
LOS
7
A4
GNDIO
LOOP
3
LOS
0
RGND
0
TNEG
6
RNEG
7
TNEG
7
RNEG
6
TNEG
1
RNEG
0
TNEG
0
RNEG
1
LOS
6
A3
A0
LOOP
4
LOS
1
LOOP
1
TPOS
6
RPOS
7
TPOS
7
RPOS
6
TPOS
1
RPOS
0
TPOS
0
RPOS
1
MODE
A2
LOOP
0
LOOP
5
MUX
LOOP
2
TCLK
6
RCLK
7
TCLK
7
RCLK
6
TCLK
1
RCLK
0
TCLK
0
RCLK
1
MCLK
A1
VCCIO
LOOP
6
LOOP
7
RV0+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
CS61880
160 FBGA
(Bottom View)
LOS
4
TMS
GNDIO
RGND
1
CS
LOS
3
TVCC
5
TVCC
4
TVCC
4
TVCC
5
TVCC
2
TVCC
3
TVCC
3
TVCC
2
RD
TXOE
TCK
VCCIO
RV1+
WR
RDY
TCLK
5
RCLK
4
TCLK
4
RCLK
5
TCLK
2
RCLK
3
TCLK
3
RCLK
2
INT
LOS
5
TDI
TRST
INTL
ALE
LOS
2
TNEG
5
RNEG
4
TNEG
4
RNEG
5
TNEG
2
RNEG
3
TNEG
3
RNEG
2
Figure 2. CS61880 160-Ball FBGA Package Pin Outs