Figure 26, Figure 25, Figure 25. parallel port timing - write; intel – Cirrus Logic CS61880 User Manual
Page 62: Multiplexed address / data bus mode
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CS61880
62
DS450PP3
ALE
WR
D[7:0]
RDY
HIGH-Z
HIGH-Z
C S
1
12
4
7
6
9
8
3
5
2
13
15
14
ADDRESS
Write Data
Figure 25. Parallel Port Timing - Write; Intel
®
Multiplexed Address / Data Bus Mode
ALE
R D
D[7:0]
RDY
HIGH-Z
HIGH-Z
C S
1
12
4
7
6
3
5
2
13
15
14
11
10
ADDRESS
Read Data
Figure 26. Parallel Port Timing - Read; Intel Multiplexed Address / Data Bus Mode
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