Jtag support – Cirrus Logic CS61880 User Manual
Page 43
CS61880
DS450PP3
43
sample address (00000 binary) needs to be written
to the
AWG Phase Address Register (17h)
Section 14.24 on page 39), and each subsequent ac-
cess (read or write) to the
(See Section 14.25 on page 39) will
automatically increment the phase sample address.
The channel address, however, remains unaffected
by the Auto-Increment mode. The
page 39) needs to be re-written in order to re-start
the phase sample address sequence from the new
phase sample address.
The AWG Broadcast function allows the same data
to be written to multiple channels simultaneously.
This is done with the use of the
(See Section 14.23 on page 39),
each bit in the AWG Broadcast Register corre-
sponds to a different channel (e.g. bit 0 is channel
0, and bit 3 is channel 3 and etc.). To use the AWG
Broadcast function MCLK must be present. When
MCLK is inactive the AWG Broadcast function is
disabled.
To write the same pulse shaping data to multiple
channels, simple set the corresponding bit to “1” in
the
before accessing the AWG
phase data register. This function only requires that
one of the eight channel addresses be written to the
AWG Phase Address Register (17h)
14.24 on page 39). During an AWG read sequence,
the bits in the AWG Broadcast Register are ig-
nored. During an AWG write sequence, the select-
ed channel or channels are specified by both the
channel address specified by the upper bits of the
AWG Phase Address Register (17h)
14.24 on page 39) and the selected channel or chan-
nels in the
During a multiple channel write the first channel
that is written to, is the channel that was addressed
by the AWG Phase Address Register. This chan-
nel’s bit in the AWG Broadcast Register can be set
to either “1” or “0”.
For a more descriptive explanation of how to use
the AWG function refer to the Application Note
AN204, How To Use The CS61880/CS61884 Arbi-
trary Waveform Generator.
16. JTAG SUPPORT
The CS61880 supports the IEEE Boundary Scan
Specification as described in the IEEE 1149.1 stan-
dards. A Test Access Port (TAP) is provided that
consists of the TAP controller, the instruction reg-
ister (IR), by-pass register (BPR), device ID regis-
ter (IDR), the boundary scan register (BSR), and
the 5 standard pins (TRST, TCK, TMS, TDI, and
TDO). A block diagram of the test access port is
shown in
. The test clock in-
put (TCK) is used to sample input data on TDI, and
shift output data through TDO. The TMS input is
used to step the TAP controller through its various
states.
The instruction register is used to select test execu-
tion or register access. The by-pass register pro-
vides a direct connection between the TDI input
and the TDO output. The device identification reg-
ister contains a 32-bit device identifier.
The Boundary Scan Register is used to support test-
ing of IC inter-connectivity. Using the Boundary
Scan Register, the digital input pins can be sampled
and shifted out on TDO. In addition, this register
can also be used to drive digital output pins to a
user defined state.