AMD Geode SC1201 User Manual
Page 245
AMD Geode™ SC1200/SC1201 Processor Data Book
245
Core Logic Module - SMI Status and ACPI Registers - Function 1
32579B
10
EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.
0: No.
1: Yes.
To enable SMI generation, set bit 2 to 1.
9
EXT_SMI1 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.
0: No.
1: Yes.
To enable SMI generation, set bit 1 to 1.
8
EXT_SMI0 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.
0: No.
1: Yes.
To enable SMI generation, set bit 0 to 1.
7
EXT_SMI7 SMI Enable. When this bit is asserted, allow EXT_SMI7 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 23 (RC) and 15 (RO).
6
EXT_SMI6 SMI Enable. When this bit is asserted, allow EXT_SMI6 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 22 (RC) and 14 (RO).
5
EXT_SMI5 SMI Enable. When this bit is asserted, allow EXT_SMI5 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 21 (RC) and 13 (RO).
4
EXT_SMI4 SMI Enable. When this bit is asserted, allows EXT_SMI4 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 20 (RC) and 12 (RO).
3
EXT_SMI3 SMI Enable. When this bit is asserted, allow EXT_SMI3 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 19 (RC) and 11 (RO).
2
EXT_SMI2 SMI Enable. When this bit is asserted, allow EXT_SMI2 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 18 (RC) and 10 (RO).
1
EXT_SMI1 SMI Enable. When this bit is asserted, allow EXT_SMI1 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 17 (RC) and 9 (RO).
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description