AMD Geode SC1201 User Manual

Page 246

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246

AMD Geode™ SC1200/SC1201 Processor Data Book

Core Logic Module - SMI Status and ACPI Registers - Function 1

32579B

0

EXT_SMI0 SMI Enable. When this bit is asserted, allow EXT_SMI0 to generate an SMI on negative-edge events.

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 16 (RC) and 8 (RO).

Offset 28h-4Fh

Not Used

Reset Value: 00h

Offset
50h-FFh

The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The pre-
ferred method is to program these registers through the F0 register space. Refer to Table 6-29 "F0: PCI Header/Bridge Con-
figuration Registers for GPIO and LPC Support" on page 190 f
or more information about these registers.

Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

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