AMD Geode SC1201 User Manual

Page 287

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AMD Geode™ SC1200/SC1201 Processor Data Book

287

Core Logic Module - USB Controller Registers - PCIUSB

32579B

Offset 10h-13h

HcInterruptEnable Register (R/W)

Reset Value = 00000000h

31

MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.

30

OwnershipChangeEnable.

0: Ignore.

1: Enable interrupt generation due to Ownership Change.

29:7

Reserved. Read/Write 0s.

6

RootHubStatusChangeEnable.

0: Ignore.

1: Enable interrupt generation due to Root Hub Status Change.

5

FrameNumberOverflowEnable.

0: Ignore.

1: Enable interrupt generation due to Frame Number Overflow.

4

UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.

3

ResumeDetectedEnable.

0: Ignore.

1: Enable interrupt generation due to Resume Detected.

2

StartOfFrameEnable.

0: Ignore.

1: Enable interrupt generation due to Start of Frame.

1

WritebackDoneHeadEnable.

0: Ignore.

1: Enable interrupt generation due to Writeback Done Head.

0

SchedulingOverrunEnable.

0: Ignore.

1: Enable interrupt generation due to Scheduling Overrun.

Note:

Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.

Offset 14h-17h

HcInterruptDisable Register (R/W)

Reset Value = 00000000h

31

MasterInterruptEnable. Global interrupt disable. A write of 1 disables all interrupts.

30

OwnershipChangeEnable.

0: Ignore.

1: Disable interrupt generation due to Ownership Change.

29:7

Reserved. Read/Write 0s.

6

RootHubStatusChangeEnable.

0: Ignore.

1: Disable interrupt generation due to Root Hub Status Change.

5

FrameNumberOverflowEnable.

0: Ignore.

1: Disable interrupt generation due to Frame Number Overflow.

4

UnrecoverableErrorEnable. This event is not implemented. All writes to this bit will be ignored.

3

ResumeDetectedEnable.

0: Ignore.

1: Disable interrupt generation due to Resume Detected.

Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)

Bit

Description

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