AMD Geode SC1201 User Manual

Page 271

Advertising
background image

AMD Geode™ SC1200/SC1201 Processor Data Book

271

Core Logic Module - Audio Registers - Function 3

32579B

1

Assert Masked Internal IRQ1.

0: Disable.

1: Enable.

0

Reserved. Must be set to 0.

Offset 20h

Audio Bus Master 0 Command Register (R/W)

Reset Value: 00h

Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

7:4

Reserved. Must be set to 0. Must return 0 on reads.

3

Read or Write Control. Sets the transfer direction of the Audio Bus Master.

0: PCI reads are performed.

1: PCI writes are performed.

This bit must be set to 0 (read), and should not be changed when the bus master is active.

2:1

Reserved. Must be set to 0. Must return 0 on reads.

0

Bus Master Control. Controls the state of the Audio Bus Master.

0: Disable.

1: Enable.

Setting this bit to 1 enables the bus master to begin data transfers.

When writing 0 to this bit, the bus master must either be paused, or reach EOT. Writing 0 to this bit while the bus master is
operating may result in unpredictable behavior (and may crash the bus master state machine). The only recovery from such
unpredictable behavior is a PCI reset.

Offset 21h

Audio Bus Master 0 SMI Status Register (RC)

Reset Value: 00h

Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

7:2

Reserved.

1

Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.

0: No.

1: Yes.

If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause
until this register is read to clear the error.

0

End of Page. Indicates if the bus master transferred data which is marked by EOP bit in the PRD table (bit 30).

0: No.

1: Yes.

Offset 22h-23h

Not Used

Offset 24h-27h

Audio Bus Master 0 PRD Table Address (R/W)

Reset Value: 00000000h

Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.

31:2

Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for Audio Bus Master 0.

When written, this register points to the first entry in a PRD table. Once Audio Bus Master 0 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.

When read, this register points to the next PRD.

1:0

Reserved. Must be set to 0.

Note:

The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.

DWORD 0:

[31:0]

= Memory Region Physical Base Address

DWORD 1:

31

= End of Table Flag

30

= End of Page Flag

29

= Loop Flag (JMP)

[28:16]

= Reserved (0)

[15:0]

= Byte Count of the Region (Size)

Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)

Bit

Description

Advertising
This manual is related to the following products: