Figure 9-57, Power-up sequencing without pwrbtn# timing diagram, Table 9-47 – AMD Geode SC1201 User Manual
Page 434
434
AMD Geode™ SC1200/SC1201 Processor Data Book
Electrical Specifications
32579B
Figure 9-57. Power-Up Sequencing Without PWRBTN# Timing Diagram
ACPI is non-functional and all ACPI outputs are undefined when the power-up sequence does not include using the power
button. SUSP# is an internal signal generated from the ACPI block. Without an ACPI reset, SUSP# can be permanently
asserted. If the USE_SUSP bit in CCR2 of GX1 module is enabled (Index C2h[7] = 1), the CPU will stop.
If ACPI functionality is desired, or the situation described above avoided, the power button must be toggled. This can be
done externally or internally. GPIO63 is internally connected to PWRBTN#. To toggle the power button with software,
GPIO63 must be programmed as an output using the normal GPIO programming protocol (see Section 6.4.1.1 "GPIO Sup-
port Registers" on page 224). GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain
active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low.
Table 9-47. Power-Up Sequence Not Using the Power Button Timing Parameters
Symbol
Parameter
Min
Max
Unit
Comments
t
1
Voltage sequence
-100
100
ms
Optimum power-up results with
t
1
= 0.
t
2
POR# inactive after V
SBL
, V
CORE
, V
SB
,
and V
IO
applied
50
ms
POR# must not glitch during
active time.
t
3
32KHZ startup time
1
s
Time required for 32 KHz oscilla-
tor and 14.318 MHz derived from
PLL6 to become stable at which
time the RTC can reliably count.
Assumes unbalanced external
circuit. See Table 5.5.2.1 "Inter-
nal Oscillator" on page 105 for
details.
t
1
V
SBL,
V
CORE
1
V
SB,
V
IO
2
POR#
t
2
1)
V
SBL
and V
CORE
should be tied together.
2)
V
SB
and V
IO
should be tied together.
t
3
32KHZ