Rockwell Automation 57C422B 2 Axis Servo Module - Manual (Page 71)

PROGRAMMING 4-43
Block tasks.
Note that two of the registers used to implement interrupts,
64 (described in section 4.33) and 4095, are used for both
the X and Y axis. To avoid any confusion, at times this
section of the manual will not follow the general pattern of
notation found in the remainder of this instruction manual
and will explicitly refer to both the X and Y axis equivalents of
the register in question instead of only the X. In other words,
where the Y equivalent is given explicitly, you will not need to
add 2048 to the register number given for the X axis to find
the Y axis equivalent of the register number. Pairs of
registers that perform one function, such as enabling
interrupts, will be shown separated by a slash. For example,
registers 72/73 refers to all of the bits in registers 72 and 73
as a group.
4.49.1 Registers 68/69: Interrupt Enable
Registers 72 and 73 [X-axis] and 2120 and 2121 [Y-axis) are
read only registers that are used by the 2-Axis module to
report motion status and fault status for the two axes on a
continuous basis. You can choose to enable a hardware
interrupt whenever any bit in registers 72/73 or 2120/2121 is
set by the module. See section 4.37 and 4.38 for more
information on these status and fault registers.
To enable interrupts, the user application program must set a
bit or bits in registers 68/69, the interrupt enable masking
registers, that corresponds, respectively, to a bit or bits in
registers 72/73. For example, if you want to enable a
hardware interrupt whenever the “axis done” bit (0) in
register 72 is set by the system, set bit 0 in register 68 to
enable the interrupt. If you wanted to enable an interrupt
whenever the “velocity error exceeded” bit (5) in register 73
was set bit the system, you would set bit 5 in register 69.
You can set multiple bits in registers 68/69. Any bit or any
combination of those bits being set by the module in the
corresponding registers (72/73) will result in a hardware
interrupt. See figures 4.48 and 4.49.