Dell PowerEdge C5230 - Manual (Page 62)

62 Using the System Setup Program
PCI Express* Errors
The hardware is programmed to generate an SMI on PCIe correctable,
uncorrectable non-fatal, and uncorrectable fatal errors. The correctable PCIe
errors are reported to the BMC as PCIe Bus Correctable errors. PCIe non-
fatal and fatal errors are reported to the BMC as PCIe Bus Uncorrectable
errors. The system event log for these errors includes the location of the
device reporting an error which includes the PCIe link number, PCI bus
number, PCI device number, and the PCI function number. An NMI is
generated for PCIe Uncorrectable errors after they are logged.
Processor Bus Error
The BIOS enables the error correction and detection capabilities of the
processors by setting appropriate bits in the processor model specific register
(MSR) and the appropriate bits inside the chipset.
In the case of unrecoverable errors on the host processor bus, proper
execution of the asynchronous error handler (usually SMI) cannot be
guaranteed and the handler cannot be relied upon to log such conditions. The
handler records the error to the system event log only if the system has not
experienced a catastrophic failure that compromises the integrity of the
handler.
Memory Bus Error
The hardware is programmed to generate an SMI on correctable data errors in
the memory array. The SMI handler records the error and the DIMM location
to the system event log. Uncorrectable errors in the memory array are mapped
to the SMI because the BMC cannot determine the location of the bad
DIMM. The uncorrectable errors may have corrupted the contents of
SMRAM. The SMI handler will log the failing DIMM number to the BMC if
the SMRAM contents are still valid. The ability to isolate the failure down to
a single DIMM may not be available on certain errors, and / or during early
POST.