Figure 1-13, Trigger bus bridge capability, Preliminary – ADLINK PXES-2780 User Manual

Page 27

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Introduction

17

PXES-2780

Figure 1-13: Trigger Bus Bridge Capability

For details regarding configuration of trigger bus bridge routing
please see “Trigger Bus” on page 34 .

Reference Clock

The PXES-2780 backplane supplies a single-ended 10MHz

reference clock (PXI_CLK10) and differential 100MHz clock
(PXIe_CLK100) to each peripheral slot for inter-module syn-

NOTE:

NOTE:

The solid circle shown represents the source of the trigger and
the transparent circle the trigger destination.

PRELIMINARY

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