ADLINK PXIe-9848 - Manual (Page 26)

16 Operations
3.2.3 FIFO and DMA Transfer For Analog Input
FIFO
One FIFO is implemented on the PXIe-9848 for analog input
data storage. FIFO depth is 32M samples/ per channel and is not
shared between all AI channels.
Bus-Mastering DMA Data Transfer
PCI Express offers dedicated bandwidth of up to 250MB/s. Unlike
the PCI bus, having parallel bus architecture dividing bandwidth
among all devices on the bus, PCI Express features peer-to-peer
architecture with dedicated data pipelining. Data can be trans-
ferred at 2.5Gb/s, which enables a theoretical 250MB/s bandwidth
per lane. With PCI Express, data bandwidth is dramatically
improved compared to the PCI bus, allowing data to be streamed
to the system faster with minimum onboard memory required.
One of the most important features of the PXIe-9848 is the PCI
Express Gen 1 x 4 interface. The PXIe-9848 is equipped with eight
100MS/s high sampling rate ADCs, generating data rates up to 1.6
GByte/s. When streaming this data from ADCs to system memory,
bandwidth remains insufficient. Data bandwidth is 1.6 GByte/s
while the PCI Express Gen 1 X4 is only up to 1 GByte/s. Reducing
the number of acquired channels or decreasing the sampling rate
enables unlimited streaming, making it useful to have a high band-
width bus interface when streaming data from ADC to system
memory.
Actual data throughput for a PC system depends on system topol-
ogy, data transfer between other devices in the system, and other
components in the system. For example, data transfer between
digitizers and host memory usually travels through a PCIe switch
before transfer to the host system. All digitizers share the band-
width available on the link between PCIe switch and the host sys-
tem.
To provide efficient data transfer, a PCI bus-mastering DMA is
essential for continuous data streaming, as it helps to achieve full
potential PCI Express bus bandwidth. The bus-mastering control-
ler releases the burden on the host CPU since data is directly