ADLINK PXIe-9848 - Manual (Page 27)

Operations 17
PXIe-9848
transferred to the host memory without intervention. Once analog
input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired
data in the onboard AD Data FIFO, and then transfers the data to
a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA data
acquisition, the sampling period and the number of conversions
needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system
memory by the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, or other, it is difficult to allocate a large continuous memory
block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into
a linked list enabling transfer of large amounts of data without
memory limitations. In non-scatter-gather mode, the maximum
DMA data transfer size is 2 MB double words (8 MB bytes); in
scatter-gather mode, there is no limitation on DMA data transfer
size aside from the physical storage capacity of the system.
Users can also link descriptor nodes circularly to achieve a multi-
buffered DMA. In the following linked list, comprising three DMA
descriptors, each descriptor contains a PCI address, PCI dual
address, transfer size, and pointer to the next descriptor.
PCI address and PCI dual address support 64-bit addresses
which can be mapped into more than 4 GB of address space.
Figure 3-2: Linked List of PCI Address DMA Descriptors
Local Memory
( FIFO)
PCI Express Bus
First PCI Address
First Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor