ADLINK PXIe-9848 - Manual (Page 7)

List of Figures vii
PXIe-9848
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±2 V Input Range
20MHz3
Figure 1-2: Analog Input Channel Bandwidth, ±2 V Input Range
100MHz3
Figure 1-3: PXIe-9848 Dimensions............................................... 7
Figure 1-4: PXIe-9848 I/O Array ................................................... 8
Figure 3-1: Analog Input Architecture of the PXIe-9848 ............. 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 17
Figure 3-3: Trigger Architecture of the PXIe-9848 ...................... 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: External Digital Trigger Configuration....................... 20
Figure 3-6: Analog Trigger Conditions ........................................ 21
Figure 3-7: Post-Trigger Acquisition ........................................... 23
Figure 3-8: Pre-trigger Acquisition .............................................. 23
Figure 3-9: Middle-trigger Acquisition ......................................... 24
Figure 3-10: Delayed Trigger Mode Acquisition............................ 24
Figure 3-11: Re-Trigger Mode Acquisition .................................... 25
Figure 3-12: PXIe-9848 Timebase Architecture............................ 25
Figure 3-13: Basic Digitizer Acquisition Timing............................. 27
Figure 3-14: Varying Sampling Rates by Adjusting Scan Interval
Counter27