ADLINK PXI-9527 - Manual (Page 36)

26 Operations
Bus-Mastering Dma Data Transfer
PCI bus-mastering DMA is essential for continuous data
streaming, as it helps to achieve full potential PCI bus band-
width and improve bus efficiency. The bus-mastering controller
controls the PCI bus, with the host CPU unburdened, since
data is directly transferred to the host memory without interven-
tion. Once analog input begins, the DMA returns control of the
program. During DMA transfer, the hardware temporarily stores
acquired data in the onboard AD Data FIFO, and then transfers
the data to a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA
data acquisition, the sampling period and number of conver-
sions need only be assigned to their specified counters. After
the AD trigger condition is met, data is transferred to the sys-
tem memory by the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Win-
dows, Linux, or other, it can be difficult to allocate a large con-
tinuous memory block. Therefore, the PCI controller provides
DMA transfer with scatter-gather function to link non-continu-
ous memory blocks into a linked list allowing transfer of large
amounts of data without being limited by memory limitations. In
non-scatter-gather mode, the maximum DMA data transfer size
is 2 MB double words (8 MB bytes); in scatter-gather mode,
there is no limitation on DMA data transfer size beyond physi-
cal storage capacity of the system. Users can also link descrip-
tor nodes circularly to achieve a multi-buffered DMA. As
shown, in a linked list comprising three DMA descriptors, each
containing a PCI address, PCI dual address, transfer size, and
the pointer to the next descriptor, PCI address and PCI dual
address support 64-bit addresses which can be mapped into
more than 4 GB of address space.