ADLINK PXI-9527 - Manual (Page 40)

30 Operations
Bus-mastering DMA Data Transfer
For analog output, data is transferred from host PC memory to
onboard FIFO by DMA transfer. Please see Section 3.2.4:
FIFO and DMA Transfer For Analog Input for a detailed
description.
3.4 Trigger Source and Trigger Mode
This section details PXI-9527 triggering operations. Since AI and
AO share the same trigger source, when their operations are
simultaneously enabled, the trigger signal is valid only when both
are ready to receive the trigger signal. For more details of pro-
gramming the PXI-9527, please refer to the software operation
manual.
3.4.1 Trigger Sources
Figure 3-4: Trigger Architecture of the PXI-9527
The PXI-9527 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger source.
The PXI-9527 supports internal software trigger, external digital
trigger, PXI_STAR trigger, PXI Trigger Bus [0.7], and SSI bus as
well as analog trigger.
Software Trigger
TRG Input
SMB Connector
Digital Trigger Input
To Internal
FPGA Circuit AI CH0 Analog
Trigger
AI CH1 Analog
Trigger
PXI In
te
rface
T
ri
g
ge
r
S
o
u
rc
e
M
ux
PXI_STAR
PXI Trigger Bus
[0..7]
T
rigger Output Mux
TRG I/O
SMB Connector
P
X
I Interf
ac
e
Digital Trigger Output
Trigger
Decision