5 adc and dac timing control, 1 timebase architecture, Adc and dac timing control – ADLINK PXI-9527 User Manual
Page 44: Timebase architecture, Figure 3-7, Post-trigger acquisition / waveform generation, Figure 3-8, Figure 3-9, Pxi-9527 timebase architecture
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Operations
Figure 3-7: Post-trigger Acquisition / Waveform Generation
Delay Trigger Mode
If delay trigger mode is configured, delay time from when the
trigger event asserts to the beginning of the acquisition and
waveform generation can be specified, as shown. Delay time is
specified by a 32-bit counter value with the counter clocking
based on the PCI clock. Accordingly, maximum delay time is
the period of PCI_CLK X (232 - 1) and minimum is the period of
PCI_CLK.
Figure 3-8: Delay Trigger Mode Acquisition / Waveform Generation
3.5 ADC and DAC Timing Control
3.5.1
Timebase Architecture
Figure 3-9: PXI-9527 Timebase Architecture
DAC CH1
ADC CH0
ADC CH1
DAC CH0
DDS
1/2
Divider
1/2
Divider
Onboard
125MHz
Oscillator
125MHz
External
PXI
10MHz
PLL
1-
to
-4
C
lo
c
k
Bu
ff
e
r
Resolution equal to
125MHz/2^ 32 =0.029Hz