ADLINK PXI-9527 - Manual (Page 45)

Operations 35
PXI-9527
To drive the sigma-delta ADC and DAC, an onboard timebase
clock is applied. The timebase clock frequency exceeds the sam-
ple rate and is produced by a DDS chip. The output frequency of
DDS chip is programmable with excellent resolution. The PXI-
9527 accepts the external 10MHz clock from the PXI backplane
for better synchronization between modules.
3.5.2 DDS Timing VS ADC/DAC Relationship
3.5.3 Timing Constraints
As described in Section 3.5.1, the ADC and DAC share a single
timebase source, that is, the output of the DDS clock. When simul-
taneous operation of ADC and DAC is implemented, it should be
considered that:
X When sampling rate of the ADC is set to before configuring
DAC, the update rate of the DAC is limited and fixed corre-
spondingly, and when update rate of the DAC is set before
configuring ADC, the sampling rate of DAC is limited and
fixed correspondingly, as shown
X Because the ADC and DAC share the same trigger source,
both AI and AO operations require coordination prior to trig-
ger event, that is, the trigger event cannot occur before AI &
AO configuration is complete
3.5.4 Filter Delay in ADC and DAC
The filter delay indicates the time required for data to propagate
through a converter. Both AI and AO channels experience filter
delay due to the filter circuitry and the architecture of the con-
verter, as shown.
Sampling
Rate
2 K - 54 kHz 54 K - 108 kHz
108 K - 216
kHz
216 K - 432 kHz
Update
Rate
1K-27 kHz 27K-54 kHz 54K-108 kHz 108K-216 kHz
DDS CLK
512 K-13.824
MHz
6.912 M-
13.824 MHz
6.912 M-
13.824 MHz
13.824 M-
27.648 MHz
Table 3-8: Timing Relationship of the ADC, DAC and DDS Clock