ADLINK cExpress-HL - Manual (Page 19)

cExpress-HL Page 19
Signal Pin # Description I/O PU/PD Comment
PCIE_RX5+
PCIE_RX5- B52
B53 PCI Express channel 5, Receive Input differential
pair. I PCIE Not supported
PCIE_CLK_REF+
PCIE_CLK_REF- A88
A89 PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes. O PCIE
3.3.7 Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE# A49
B48 PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
EXCD0_PERST#
EXCD1_PERST# A48
B47 PCI ExpressCard: reset O 3.3V
3.3.8 LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1# B8
B9 LPC serial DMA request I 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V
3.3.9 USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0- A46
A45 USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB1+
USB1- B46
B45 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB2+
USB2- A43
A42 USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB3+
USB3- B43
B42 USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB4+
USB4- A40
A39 USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB5+
USB5- B40
B39 USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB6+
USB6- A37
A36 USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB7+
USB7- B37
B37 USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier