Altera ALTDQ_DQS2 - Manual (Page 15)

Parameter Editor GUI Setting
CLI Parameter
Description
Name
Legal Values
Name
Legal
Values (1)
Treat the capture
strobe enable as a
half-rate signal
— USE_HALF_RATE_DQS_
ENABLE
true
false
This setting doubles the
width of the capture
strobe enable bus on the
FPGA side and clocks the
FPGA side interface using
the half-rate clock input.
DQS enable phase
setting
0 degrees
45 degrees
90 degrees
135 degrees DQS_ENABLE_PHASE_
SETTING
0
1
2
3
This setting specifies the
value of phase shift to shift
the full-rate clock signal
that drives the capture
strobe enable block.
The default value is 0
degrees (
0
).
Output Strobe
Generate output
strobe
— USE_OUTPUT_STROBE
true
false
This setting generates an
output strobe signal based
on the OE signal and the
full-rate clock. This setting
is enabled by default.
Make capture
strobe bidirec‐
tional
— USE_BIDIR_STROBE
true
false
This setting enables the
bidirectional capture
strobe (capture strobe and
output strobe is on the
same port).
This setting is disabled by
default.
Differential/
complementary
output strobe
— DIFFERENTIAL_
OUTPUT_STROBE
true
false
This setting enables either
the differential or
complementary output
strobe.
This setting is disabled by
default.
(1) All CLI parameter values are type string, therefore you must enclose the values in double quotes.
UG-01089
2014.12.17
ALTDQ_DQS2 Parameter Settings 15
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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