Altera ALTDQ_DQS2 - Manual (Page 45)

Legend in I/O Configu‐
ration Block Bit
Sequence for Arria V
GZ and Stratix V
Devices on page 40
Bit Bit Name Description
K 33..32 dqoutputphasesetting Connects to the phasectrlin port
of the clock phase select (in the
DQ output path) to select
between phase shifts of 0°, 45°,
90°, and 135°.
DQ leveling clock select. n Use
this bit to level the DQ write
output.
— 35..34 dqoutputpowerdown Unconfigurable bits.
Always set bits to its default
value.
L 36 dqoutputphaseinvert Connects to the phaseinvertctrl
port of the clock phase select (in
the DQ output path) to select
between the non-inverted and
inverted output.
This setting allows the phase
output from the delay chain to be
inverted to gain additional
phases.
— 40..37 resyncinputphasesetting
resyncinputpowerdown
resyncinputphaseinvert Unconfigurable bits.
Always set bits to its default
value.
M 42..41 postamblephasesetting Connects to the phasectrlin port
of the clock phase select (for the
DQS enable control block) to
select between phase shifts of 0°,
45°, 90°, and 135°.
Use this clock phase select block
to level the postamble
(dqsenablein signal at the DQS
enable control block).
— 44..43 postamblepowerdown Unconfigurable bits.
Always set bits to its default
value.
UG-01089
2014.12.17
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices 45
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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