Altera ALTDQ_DQS2 - Manual (Page 36)

Table 11: ALTDQ_DQS2 Dynamic Configuration Ports
Port name Type Width Description
config_clock_in Input 1 The ALTDQ_DQS2 dynamic
configuration interface consists
of this input port.
Receives the clock signal to
clock all dynamic configuration
blocks. You can connect this
port to a clock pin, or the PLL
clock output port.
This is the clock signal. All other
input signals must be treated as
synchronous to this clock.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
config_data Input 1 The ALTDQ_DQS2 dynamic
configuration interface consists
of this input port.
The 1-bit serial input through
which data is scanned into the
calibration blocks. It is common
to all configuration blocks, but it
will only be scanned into
calibrations blocks whose enable
input is asserted.
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
config_io_ena[] Input n An input port that controls the
enable input on the DQ I/O
configurations. Receives the
clock enable signal for the I/O
configuration block.
Refer to
Dynamic Reconfigura‐
tion for ALTDQ_DQS2 on
page 38
This port is supported in Arria
V, Cyclone V, and Stratix V
devices.
36 ALTDQ_DQS2 Dynamic Configuration Ports
UG-01089
2014.12.17
Altera Corporation ALTDQ_DQS2 IP Core User Guide
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