Altera ALTDQ_DQS2 User Manual
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8. To view the simulation results, on the Tools menu, select Run Simulation Tool and then click RTL
Simulation.
For a successful simulation, you may need to manually change alterapll.vo to alterapll.v in the auto-
generated top_run_msim_rtl_verilog.do file.
9. Before running the Fitter, ensure that the following settings are done in the Assignment Editor.
• I/O Standard
• Input Termination
• Output Termination
• DQ Group
• Location assignment for strobe pin—this helps the Fitter to fit the related DQ pins in the
appropriate l/O sub-banks. You can then back-annotate the locations if desired.
The following figure shows an example setting in the Assignment Editor and the Pin Planner results:
Figure 53: Assignment Editor Window
UG-01089
2014.12.17
Setting Up NativeLink and Simulation Settings
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ALTDQ_DQS2 IP Core User Guide
Altera Corporation