Altera ALTDQ_DQS2 - Manual (Page 97)

--component-param=USE_OUTPUT_STROBE=”False” --component-
param=DQS_PHASE_SETTING=”3”
This command generates two files—my_dqdqs2.v and my_dqdqs2_altdq_dqs2.sv. The my_dqdqs2.v
file contains the
my_dqdqs2
top-level module, and the my_dqdqs2_altdq_dqs2.sv file contains the
source code. The files are in Verilog HDL format.
The
ip-generate
command generates the ports for the instance based on the parameter values.
Related Information
• ALTDQ_DQS2 Ports on page 24
• ALTDQ_DQS2 Parameter Settings on page 11
Document Revision History
Table 24: Document Revision History
Date Version Changes
December 2014 2014.12.17 Updated the description for
write_strobe_
clock_in
signal to explain that the signal is a
full-rate input clock when you set the IP type to
Input for Arria V and Cyclone V devices.
UG-01089
2014.12.17
Document Revision History 97
ALTDQ_DQS2 IP Core User Guide Altera Corporation
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