Altera Avalon Verification IP Suite - Manual (Page 108)

May 2011 Altera Corporation Avalon Verification IP Suite User Guide
4. Avalon-ST Sink BFM with Avalon-ST
API Wrapper
The Avalon-ST Sink BFM with Avalon-ST API Wrapper provides VHDL support for
the Avalon-ST Sink BFM. You can use the Avalon-ST Sink BFM with Avalon-ST API
Wrapper in HDL simulators that support mixed language simulation.
1
The API wrapper is only supported in SOPC Builder. The API wrapper cannot be
generated in Qsys to create VHDL simulation models.
The Avalon-ST Sink BFM with Avalon-ST API Wrapper component is implemented in
SystemVerilog and uses an API wrapper to cast the Avalon-ST Sink BFM’s method
calls and returns into signals that are carried on the call and return interface ports. The
wrapper is necessary because VHDL can only access ports and does not support the
method calls used in the Avalon-ST Sink BFM.
Figure 4–1 provides a high-level view
of this component.
In Figure 4–1 , the API call interface and Avalon-ST call and return interface operate in
separate clock domains with av_clk synchronizing the FPGA logic and api_clk
synchronizing the Avalon-ST translation interface. The Avalon-ST interface, which is
not part of the actual hardware design, operates at a much higher frequency than the
Avalon-ST Sink BFM interface.
Figure 4–1. Avalon-ST Sink BFM with Avalon-ST Wrapper
Avalon-ST Sink BFM Translator
API Methods
(Tasks & Functions
SystemVerilog)
API Calls and Returns
Ports to References
Avalon-ST Source
VHDL
Testbench Using Mixed-Language Simulator
Avalon-ST
Avalon-ST
Function
Calls
Avalon-ST
Function
Returns
Avalon-ST Sink BFM with Avalon-ST Wrapper
API Call
Interface
Test Program
VHDL