Altera Avalon Verification IP Suite - Manual (Page 169)

2–2 Chapter 2: Qsys Tutorial
Verifying Avalon-ST DUT
Avalon Verification IP Suite User Guide May 2011 Altera Corporation
The test flow includes the following steps:
1. The test program initializes the BFMs.
2. The test program runs the following three parallel processes:
a. Creates and sends four test transactions to the source BFM. The transactions
consists of six Avalon-ST signals— data , channel , error , empty , startofpacket ,
endofpacket , and a BFM related parameter, idle . The Avalon-ST Source BFM
drives the transactions to the Avalon-ST Single-Clock FIFO buffer. In addition,
the Avalon-ST Source BFM keeps a local copy of the transactions for future
reference, and prints the transaction values in the ModelSim transcript console.
b. Controls the Avalon-ST Sink BFM. When the Avalon-ST Sink BFM receives a
transaction, the Avalon-ST Sink BFM reads the transaction values, prints the
transaction values on the ModelSim transcript console, and compares the
values it receives to the values from the Avalon-ST Source BFM. The Avalon-ST
Sink BFM reports any mismatch in values as failures. During this process, the
Avalon-ST Sink BFM backpressures the Avalon-ST Single-Clock FIFO buffer.
c. Measures the response latency when the Avalon-ST Single-Clock FIFO buffer
backpressures the Avalon-ST Source BFM. The Avalon-ST Source BFM prints
the transaction values on the ModelSim transcript console.
3. The parallel processes terminate when the Avalon-ST Source and Sink BFM
transaction queues are empty and all four transactions are complete.
4. The test program prints a pass or fail message in the ModelSim transcript console.
The test passes if all of the transactions that the Avalon-ST Source BFM sends to
the Avalon-ST Single-Clock FIFO buffer match the transactions that the Avalon-ST
Sink BFM receives from the Avalon-ST Single-Clock FIFO buffer.
Setting up the Test
This section describes the steps required to build the test system in Qsys. In this
section you generate a testbench system in Qsys for the DUT. The DUT in this tutorial
is the Avalon-ST Single-Clock FIFO buffer.
Creating a Qsys System for the DUT
Before you run the design file, unzip the ug_avalon_verification.zip file to a working
directory on your hard drive. This location is referred to as <working_directory>.
1. On the Windows Start menu, point to All Programs, then Altera, and click
Quartus II ><version number> to run the Quartus II software.
2. On the File menu, click Open. Select st_bfm_project.qpf located in
<working_directory>\ug_avalon_verification\qsys.
3. On the Tools menu, click Qsys.
4. When prompted to open a file, select st_bfm_qsys_tutorial.qsys, and click Open
to open the blank Qsys system provided.
5. Type “sc fifo” in the search field located in the Component Library panel. From
the search results, double-click on the Avalon-ST Single Clock FIFO component.