Altera Avalon Verification IP Suite - Manual (Page 161)

Chapter 1: SOPC Builder Tutorial 1–5
Verifying Avalon-MM Slave DUT
May 2011 Altera Corporation Avalon Verification IP Suite User Guide
Connecting and Generating the SOPC Builder System
To connect and generate the SOPC Builder system, follow these steps:
1. Connect the master_bfm m0 Avalon-MM master port to the onchip_mem s1
Avalon-MM slave port using the following procedure:
a. Click on the m0 port then hover in the Connections column to display possible
connections.
b. Click on the open dot at the intersection of the onchip_mem s1 port and the
master_bfm m0 to create a connection.
2. Click Generate. Save the system if you are prompted to do so.
Running the Simulation
In this section you run a simulation in the ModelSim-Altera software on the testbench
that you created. To complete this simulation you use the test program provided in
the design files to provide simulation stimulus.
1. Start the ModelSim-Altera software.
2. On the File menu click Change Directory.
3. Navigate to
<working_directory>\ug_avalon_verification\sopc_builder\tutorial_master_bfm
and click OK.
4. On the Compile menu, click Compile Options.
5. Click the Verilog & SystemVerilog tab.
6. In the Language Syntax box, select Use SystemVerilog and click OK.
7. On the File menu, click Load.
1 Ensure you activate your cursor on the ModelSim-Altera Transcript
window, otherwise the Load function is disabled.
8. Select script.do, and click Open. The script creates a new working library,
compiles all source files, runs simulation, and loads signals into the ModelSim
waveform viewer.
1 If you are running ModelSim-SE you must use the -novopt option to prevent
ModelSim from optimizing the design, making the signals specified in for the wave
viewer unavailable.