Chapter 9 vhdl slave bfm, Slave bfm protocol support, Slave timing and events – Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite User Manual
Page 213: Slave bfm configuration
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
213
April 2014
Chapter 9
VHDL Slave BFM
This chapter provides information about the VHDL slave BFM. The BFM has an API that
contains procedures to configure the BFM and to access the “
during the lifetime of the transaction.
Slave BFM Protocol Support
The AXI4-Lite slave BFM supports the AMBA AXI4 protocol with restrictions detailed in
“
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following slave
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.
Slave BFM Configuration
The slave BFM supports the full range of signals defined for the AMBA AXI Protocol
Specification. The BFM has parameters that you can use to configure the widths of the address
and data signals and transaction fields to configure timeout factors, setup and hold times, and so
on.
You can change the address and data signals widths from their default settings by assigning
them new values, usually performed in the top-level module of the test bench. These new values
are then passed into the slave BFM via a parameter port list of the slave BFM component.
lists the parameter names for the address and data signals, and their default values.
Note