Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 395)

SystemVerilog Test Programs
SystemVerilog AXI4-Lite Slave BFM Test Program
Mentor Verification IP AE AXI4-Lite User Guide, V10.3 395
April 2014
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_read_addr_ready(1'b0);
join_none
bfm.get_read_addr_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_read_addr_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.ARVALID === 1'b1) && (bfm.ARREADY === 1'b1)));
end
fork
bfm.execute_read_addr_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);
fork
bfm.execute_read_addr_ready(1'b1);
join_none
seen_valid_ready = 1'b0;
end
end
endtask
// Task : handle_write_data_ready
// This method assert/de-assert the write data channel ready signal.
// Assertion and de-assertion is done based on following variable's
value:
// m_wr_data_phase_ready_delay
// slave_ready_delay_mode
task automatic handle_write_data_ready;
bit seen_valid_ready;
int tmp_ready_delay;
axi4_slave_ready_delay_mode_e tmp_mode;
forever
begin
wait(m_wr_data_phase_ready_delay > 0);
tmp_ready_delay = m_wr_data_phase_ready_delay;
tmp_mode = slave_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_write_data_ready(1'b0);