Altera Mentor Verification IP Altera Edition AMBA AXI4-Lite - Manual (Page 94)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3 94
SystemVerilog Monitor BFM
Monitor BFM Configuration
April 2014
AXI4_CONFIG_BURST_TIMEOUT_FACTOR The maximum delay between the
individual phases of a read/write
transaction in clock cycles. Default:
10000.
AXI4_CONFIG_MAX_LATENCY_
AWVALID_ASSERTION_TO_AWREADY The maximum timeout duration from
the assertion of AWVALID to the
assertion of AWREADY in clock
periods. Default: 10000.
AXI4_CONFIG_MAX_LATENCY_ARVALID_
ASSERTION_TO_ARREADY The maximum timeout duration from
the assertion of ARVALID to the
assertion of ARREADY in clock
periods. Default: 10000.
AXI4_CONFIG_MAX_LATENCY_RVALID_
ASSERTION_TO_RREADY The maximum timeout duration from
the assertion of RVALID to the
assertion of RREADY in clock
periods. Default: 10000.
AXI4_CONFIG_MAX_LATENCY_BVALID_
ASSERTION_TO_BREADY The maximum timeout duration from
the assertion of BVALID to the
assertion of BREADY in clock
periods. Default: 10000.
AXI4_CONFIG_MAX_LATENCY_WVALID_
ASSERTION_TO_WREADY The maximum timeout duration from
the assertion of WVALID to the
assertion of WREADY in clock
periods. Default: 10000.
Slave Attributes
AXI4_CONFIG_SLAVE_START_ADDR Configures the start address map for
the slave.
AXI4_CONFIG_SLAVE_END_ADDR Configures the end address map for
the slave.
Monitor Attributes
AXI4_CONFIG_AXI4LITE_axi4 Configures the AXI4 monitor BFM to
be AXI4-Lite compatible.
0 = disabled (default)
1 = enabled
Error Detection
AXI4_CONFIG_ENABLE_ALL_ASSERTIONS Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
Table 5-2. AXI Monitor BFM Configuration (cont.)
Configuration Field Description